The present invention relates generally to integrated circuit simulation and testing, and more particularly, to systems, methods and apparatus for analyzing simulations of power grid performance in an integrated circuit simulation.
Integrated circuit design has many phases one such phase is the simulation of the design. During the simulation phase, the operation of the integrated circuit is simulated including, for example, simulated logic processing, signal transmission and signal reception. The timing of the integrated circuit design is also simulated.
The simulation of the integrated circuit is performed in a computer known as a test bench. The test bench also includes software for testing the operations of the simulated integrated circuit.
One of the operational aspects of the integrated circuit simulation that is tested is the power grid loads and voltage drops at certain nodes throughout the integrated circuit design. The load on the power grid of the integrated circuit is determined by the number of devices coupled to and drawing power from the power grid and the operation of those devices at the time the test.
By way of example, each device typically draws maximum current when the device changes states. Therefore, the maximum load and the corresponding voltage drop on the power grid is a related to the operational timing of the devices coupled to the power grid. The relative loads and corresponding voltage drops are therefore determined at the selected time intervals during the simulation.
The number of devices on an integrated circuit is ever increasing. Present generations of integrated circuits have millions (and even billions) of devices. The requirement of simulating the local loads and corresponding voltage drops caused by the operations of millions of devices can require several days for the test bench to complete. Further, the simulation and power grid analysis must be repeated each time the integrated circuit design is modified.
The power grid analysis consumes too much time and significantly increases the design cycle time for integrated circuits. In view of the foregoing, there is a need for a system, method and apparatus for reducing the time required for the power grid analysis.